Generally, all chip packages have a bonding wire, chip packages that adopt substrates also have substrate wiring, and for chips adopting other packages, other wiring for connection inevitably exists from a chip bonding pad to an external path of the chip. The bonding wire, the substrate wiring, and other wiring for connection all have a parasitic wiring resistance.
For a power supply chip, because the power supply chip has multiple outputs, and each output carries a large load output current, a parasitic resistance caused by a package and wiring on a Printed Circuit Board (PCB) generates a relatively large voltage drop. With the increase of an output current, the parasitic resistance linearly generates a larger voltage drop, therefore, load regulation of the power supply chip is seriously affected, resulting in a deviation from a desired rated output voltage.
In order to improve the load regulation of the power supply chip, in the prior art, multiple bonding wires connected in parallel are used, or a single bonding wire or a single chip pin is used as a feedback wire, so as to effectively reduce an effect of the bonding wire and the substrate wiring on the output voltage, and further improve the load regulation of the power supply chip.
In the implementation of the present invention, the inventor finds that the prior art has at least the following problems.
When the load regulation of the power supply chip is improved, the number of the bonding wires of the power supply chip or additional chip pins may be increased, so that the cost of the power supply chip is increased.